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bopomofo

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最近给 HC32F460 烧程序时，出现了烧录失败的现象。

操作流程：

  • 在引导程序的 icg.h 文件中配置开启 SWDT 看门狗
  • 烧录引导程序
  • 烧录应用程序
  • 读取整个芯片的镜像
  • 把读取出来的镜像再烧回去

诡异的是，最后一步总是失败。

后面又进行了详细的测试：

测试记录 编程算法 SWDT 烧录结果
1 旧版 关闭
或者延长狗叫时间		 烧录成功
2 旧版 开启 在烧录回去之前，做一次整片擦除，但是不断电：烧录失败
在烧录回去之前，做一次整片擦除，断电再上电：烧录成功
3 新版 X 均可烧录成功

猜测应该是编程算法在烧录过程中没有屏蔽 SWDT 所致，更换新版编程算法即可解决。

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JLink info:
------------
DLL: V7.50 , compiled Jul  1 2021 17:37:28
Firmware: J-Link V9 compiled May  7 2021 16:26:12
Hardware: V9.60
S/N : 69667985
Feature(s) : RDI, GDB, FlashDL, FlashBP, JFlash

* JLink Info: Found SW-DP with ID 0x2BA01477
* JLink Info: DPIDR: 0x2BA01477
* JLink Info: Scanning AP map to find all available APs
* JLink Info: AP[1]: Stopped AP scan as end of AP map has been reached
* JLink Info: AP[0]: AHB-AP (IDR: 0x24770011)
* JLink Info: Iterating through AP map to find AHB-AP to use
* JLink Info: AP[0]: Core found
* JLink Info: AP[0]: AHB-AP ROM base: 0xE00FF000
* JLink Info: CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
* JLink Info: Found Cortex-M4 r0p1, Little endian.
* JLink Info: FPUnit: 6 code (BP) slots and 2 literal slots
* JLink Info: CoreSight components:
* JLink Info: ROMTbl[0] @ E00FF000
* JLink Info: ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7
* JLink Info: ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
* JLink Info: ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
* JLink Info: ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
* JLink Info: ROMTbl[0][4]: E0040000, CID: B105900D, PID: 000BB9A1 TPIU
ROMTableAddr = 0xE00FF000
* JLink Info: Reset: Halt core after reset via DEMCR.VC_CORERESET.
* JLink Info: Reset: Reset device via AIRCR.SYSRESETREQ.
* JLink Info: Reset: S_RESET_ST never gets cleared. CPU seems to be kept in reset forever.
* JLink Info: Reset: Using fallback: Reset pin.
* JLink Info: Reset: Halt core after reset via DEMCR.VC_CORERESET.
* JLink Info: Reset: Reset device via reset pin
* JLink Info: Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
* JLink Info: Reset: Reconnecting and manually halting CPU.
* JLink Info: Found SW-DP with ID 0x2BA01477
* JLink Info: DPIDR: 0x2BA01477
* JLink Info: AP map detection skipped. Manually configured AP map found.
* JLink Info: AP[0]: AHB-AP (IDR: Not set)
* JLink Info: AP[0]: Core found
* JLink Info: AP[0]: AHB-AP ROM base: 0xE00FF000
* JLink Info: CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
* JLink Info: Found Cortex-M4 r0p1, Little endian.
* JLink Info: CPU could not be halted
* JLink Info: Reset: Core did not halt after reset, trying to disable WDT.
* JLink Info: Reset: Halt core after reset via DEMCR.VC_CORERESET.
* JLink Info: Reset: Reset device via reset pin
* JLink Info: Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
* JLink Info: Reset: Reconnecting and manually halting CPU.
* JLink Info: Found SW-DP with ID 0x2BA01477
* JLink Info: DPIDR: 0x2BA01477
* JLink Info: AP map detection skipped. Manually configured AP map found.
* JLink Info: AP[0]: AHB-AP (IDR: Not set)
* JLink Info: AP[0]: Core found
* JLink Info: AP[0]: AHB-AP ROM base: 0xE00FF000
* JLink Info: CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
* JLink Info: Found Cortex-M4 r0p1, Little endian.
* JLink Info: CPU could not be halted
* JLink Info: Reset: Failed. Toggling reset pin and trying reset strategy again.
* JLink Info: Found SW-DP with ID 0x2BA01477
* JLink Info: DPIDR: 0x2BA01477
* JLink Info: AP map detection skipped. Manually configured AP map found.
* JLink Info: AP[0]: AHB-AP (IDR: Not set)
* JLink Info: AP[0]: Core found
* JLink Info: AP[0]: AHB-AP ROM base: 0xE00FF000
* JLink Info: CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
* JLink Info: Found Cortex-M4 r0p1, Little endian.
* JLink Info: Reset: Halt core after reset via DEMCR.VC_CORERESET.
* JLink Info: Reset: Reset device via AIRCR.SYSRESETREQ.
* JLink Info: Reset: S_RESET_ST never gets cleared. CPU seems to be kept in reset forever.
* JLink Info: Reset: Using fallback: Reset pin.
* JLink Info: Reset: Halt core after reset via DEMCR.VC_CORERESET.
* JLink Info: Reset: Reset device via reset pin
* JLink Info: Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
* JLink Info: Reset: Reconnecting and manually halting CPU.
* JLink Info: Found SW-DP with ID 0x2BA01477
* JLink Info: DPIDR: 0x2BA01477
* JLink Info: AP map detection skipped. Manually configured AP map found.
* JLink Info: AP[0]: AHB-AP (IDR: Not set)
* JLink Info: AP[0]: Core found
* JLink Info: AP[0]: AHB-AP ROM base: 0xE00FF000
* JLink Info: CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
* JLink Info: Found Cortex-M4 r0p1, Little endian.
* JLink Info: CPU could not be halted
* JLink Info: Reset: Core did not halt after reset, trying to disable WDT.
* JLink Info: Reset: Halt core after reset via DEMCR.VC_CORERESET.
* JLink Info: Reset: Reset device via reset pin
* JLink Info: Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
* JLink Info: Reset: Reconnecting and manually halting CPU.
* JLink Info: Found SW-DP with ID 0x2BA01477
* JLink Info: DPIDR: 0x2BA01477
* JLink Info: AP map detection skipped. Manually configured AP map found.
* JLink Info: AP[0]: AHB-AP (IDR: Not set)
* JLink Info: AP[0]: Core found
* JLink Info: AP[0]: AHB-AP ROM base: 0xE00FF000
* JLink Info: CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
* JLink Info: Found Cortex-M4 r0p1, Little endian.
* JLink Info: CPU could not be halted
* JLink Info: CPU could not be halted
***JLink Error: Failed to halt CPU.
* JLink Info: CPU could not be halted
Error: Flash Download failed  -  Target DLL has been cancelled
Flash Load finished at 09:01:53

* JLink Info: Reset: S_RESET_ST never gets cleared. CPU seems to be kept in reset forever.

很可能是外部复位电路失效，导致复位引脚被拉低，进而导致内核一直处于复位状态。

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在《参考手册》第六章〈初始化配置〉中，八个初始化配置寄存器的复位值是不定的，华大对此的处理方式很巧妙（但是也给移植埋下了一个大坑）：

hc32f460_icg.h
/*!< ICG0 register value */
#define ICG0_REGISTER_CONSTANT                  (((uint32_t)ICG0_WDT_REG_CONFIG << 16)  | \
                                                 ((uint32_t)ICG0_SWDT_REG_CONFIG)       | \
                                                 ((uint32_t)0xE000E000ul))
/*!< ICG1 register value */
#define ICG1_REGISTER_CONSTANT                  (((uint32_t)ICG1_NMI_REG_CONFIG << 24)  | \
                                                 ((uint32_t)ICG1_VDU0_REG_CONFIG << 16) | \
                                                 ((uint32_t)ICG1_HRC_REG_CONFIG)        | \
                                                 ((uint32_t)0x03F8FEFEul))
/*!< ICG2~7 register reserved value */
#define ICG2_REGISTER_CONSTANT                  ((uint32_t)0xFFFFFFFFul)
#define ICG3_REGISTER_CONSTANT                  ((uint32_t)0xFFFFFFFFul)
#define ICG4_REGISTER_CONSTANT                  ((uint32_t)0xFFFFFFFFul)
#define ICG5_REGISTER_CONSTANT                  ((uint32_t)0xFFFFFFFFul)
#define ICG6_REGISTER_CONSTANT                  ((uint32_t)0xFFFFFFFFul)
#define ICG7_REGISTER_CONSTANT                  ((uint32_t)0xFFFFFFFFul)
hc32f460_icg.c
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
const uint32_t u32ICG[] __attribute__((section(".icg_sec"))) =
#elif defined (__CC_ARM)
const uint32_t u32ICG[] __attribute__((at(0x400))) =
#elif defined (__ICCARM__)
__root const uint32_t u32ICG[] @ 0x400 =
#else
#error "unsupported compiler!!"
#endif
{
    /* ICG 0~ 3 */
    ICG0_REGISTER_CONSTANT,
    ICG1_REGISTER_CONSTANT,
    ICG2_REGISTER_CONSTANT,
    ICG3_REGISTER_CONSTANT,
    /* ICG 4~ 7 */
    ICG4_REGISTER_CONSTANT,
    ICG5_REGISTER_CONSTANT,
    ICG6_REGISTER_CONSTANT,
    ICG7_REGISTER_CONSTANT,
};

通过定义常量的方式，在程序加载阶段，将数据 load 至指定的寄存器。

避坑指北

如果项目由 bootloader 和 app 两部分组成，那么只能在 bootloader 中添加上述源文件，在 app 中不能添加该文件，否则会出现异常。

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beep...领导要求每天写日报，但是我不太想写，于是就有了本段代码。

# 一键生成日报 V2.0.0
import os
import re
import datetime
from datetime import timedelta
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2022年09月01日于武汉

flowchart TB
%%{init: { "flowchart": { "curve": "basis" } } }%%
R0[智能融合终端<br>SCU]
R0--->N1[断路器<br>9]
R0--->N2[断路器<br>16]
N1--->N1.1[断路器<br>7]
N1--->N1.2[断路器<br>6]
N1--->N1.3[断路器<br>10]
N1--->N1.4[断路器<br>12]
N2--->N2.1[断路器<br>18]
N2--->N2.2[断路器<br>19]
N2--->N2.3[断路器<br>14]
N1.1--->N1.1.1[断路器<br>3]
N1.1--->N1.1.2[断路器<br>4]
N1.1--->N1.1.3[断路器<br>5]
N1.2--->N1.2.1[断路器<br>8]
N1.2--->N1.2.2[断路器<br>11]
N1.3--->N1.3.1[断路器<br>2]
N2.2--->N2.2.1[断路器<br>13]
N2.2--->N2.2.2[断路器<br>17]
N1.1.1--->N1.1.1.1[断路器<br>0]
N1.2.2--->N1.2.2.1[断路器<br>1]
N2.2.2--->N2.2.2.1[断路器<br>15]
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